3893 search results - page 269 / 779 » Execution Architectures and Compilation |
207
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ANSS
2007
IEEE
15 years 11 months ago
2007
IEEE
This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many in...
186
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ICS
2009
Tsinghua U.
16 years 2 months ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
181
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ICPP
2007
IEEE
16 years 1 months ago
2007
IEEE
As multi-core microprocessors are becoming widely adopted, the need to extract thread-level parallelism (TLP) from single-threaded applications in a seamless fashion increases. In...
170
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ISCAS
2006
IEEE
16 years 1 months ago
2006
IEEE
Abstract— NnSP is a stream-based programmable and codelevel statically reconfigurable processor for realization of neural networks in embedded systems. NnSP is provided with a n...
208
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ERLANG
2004
ACM
16 years 19 days ago
2004
ACM
Erlang is a concurrent functional language designed for developing large-scale, distributed, fault-tolerant systems. The primary implementation of the language is the Erlang/OTP s...