123 search results - page 8 / 25 » Experimenting with buffer sizes in routers |
208
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VLSID
2004
IEEE
16 years 7 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
190
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ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
175
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SIPS
2007
IEEE
16 years 25 days ago
2007
IEEE
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (...
172
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TRIDENTCOM
2006
IEEE
16 years 16 days ago
2006
IEEE
—In this paper, we investigate the applicability of simulation and emulation for denial of service (DoS) attack experimentation. As a case study, we consider low-rate TCP-targete...
148
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ISCC
2006
IEEE
16 years 17 days ago
2006
IEEE
Famous rule-of-thumb states that a buffer sized at B = RTT × BW, where RTT is the average round trip time and BW is the bandwidth of output link is necessary in order to achieve ...