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ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
15 years 11 months ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
DAC
2009
ACM
15 years 11 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
ACMICEC
2006
ACM
117views ECommerce» more  ACMICEC 2006»
15 years 10 months ago
Practical secrecy-preserving, verifiably correct and trustworthy auctions
We present a practical protocol based on homomorphic cryptography for conducting provably fair sealed-bid auctions. The system preserves the secrecy of the bids, even after the an...
David C. Parkes, Michael O. Rabin, Stuart M. Shieb...
ATVA
2008
Springer
131views Hardware» more  ATVA 2008»
15 years 9 months ago
Computation Tree Regular Logic for Genetic Regulatory Networks
Model checking has proven to be a useful analysis technique not only for concurrent systems, but also for the genetic regulatory networks (Grns) that govern the functioning of livi...
Radu Mateescu, Pedro T. Monteiro, Estelle Dumas, H...
DSN
2005
IEEE
15 years 9 months ago
Experimental Evaluation of the QoS of Failure Detectors on Wide Area Network
This paper describes an experiment performed on Wide Area Network to assess and fairly compare the Quality of Service provided by a large family of failure detectors. Failure dete...
Lorenzo Falai, Andrea Bondavalli