610 search results - page 101 / 122 » Fast Modular Reduction |
149
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
169
Voted
SC
2000
ACM
15 years 10 months ago
2000
ACM
We report on our work in developing a fine-grained multithreaded solution for the communicationintensive Conjugate Gradient (CG) problem. In our recent work, we developed a simpl...
167
Voted
IPPS
1998
IEEE
15 years 10 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
210
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3DIM
1997
IEEE
15 years 10 months ago
1997
IEEE
Geometric fusion of multiple sets of overlapping surface measurements is an important problem for complete 3D object or environment modelling. Fusion based on a discrete implicit ...
174
Voted
ICDCS
2010
IEEE
15 years 10 months ago
2010
IEEE
This paper proposes LTNC, a new recoding algorithm to build low complexity network codes. At the core of LTNC is a decentralized version of LT codes that allows the use of fast be...