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ASPDAC
1998
ACM
119views Hardware» more  ASPDAC 1998»
15 years 10 months ago
Integer Programming Models for Optimization Problems in Test Generation
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
João P. Marques Silva
CLUSTER
2004
IEEE
15 years 10 months ago
Improved message logging versus improved coordinated checkpointing for fault tolerant MPI
Fault tolerance is a very important concern for critical high performance applications using the MPI library. Several protocols provide automatic and transparent fault detection a...
Pierre Lemarinier, Aurelien Bouteiller, Thomas H&e...
ISCAS
1999
IEEE
105views Hardware» more  ISCAS 1999»
15 years 10 months ago
Configuration self-test in FPGA-based reconfigurable systems
An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for...
W. Quddus, Abhijit Jas, Nur A. Touba
EVOW
1999
Springer
15 years 10 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
OPODIS
2007
15 years 8 months ago
Self-stabilizing and Byzantine-Tolerant Overlay Network
Network overlays have been the subject of intensive research in recent years. The paper presents an overlay structure, S-Fireflies, that is self-stabilizing and is robust against ...
Danny Dolev, Ezra N. Hoch, Robbert van Renesse