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» Fault tolerant nanoelectronic processor architectures
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PPOPP
2005
ACM
16 years 4 days ago
Fault tolerant high performance computing by a coding approach
As the number of processors in today’s high performance computers continues to grow, the mean-time-to-failure of these computers are becoming significantly shorter than the exe...
Zizhong Chen, Graham E. Fagg, Edgar Gabriel, Julie...
171
Voted
ICPPW
1999
IEEE
15 years 11 months ago
A Group Communication Protocol for CORBA
Group communication protocols are used in fault-tolerant systems to maintain strong replica consistency. The FaultTolerant Multicast Protocol (FTMP) described here is a group comm...
Louise E. Moser, P. M. Melliar-Smith, Ruppert R. K...
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
13 years 9 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
16 years 26 days ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
SRDS
2007
IEEE
16 years 25 days ago
The Fail-Heterogeneous Architectural Model
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
Marco Serafini, Neeraj Suri