Sciweavers

1563 search results - page 229 / 313
» Flexible instruction processors
Sort
View
ICMCS
2008
IEEE
336views Multimedia» more  ICMCS 2008»
16 years 1 months ago
SIMD optimization of the H.264/SVC decoder with efficient data structure
H.264/scalable video coding (SVC) is a new compression technique that can adapt to various network environments and applications. However, despite its outstanding performance, H.2...
Joohyun Lee, Gwanggil Jeon, Sangjun Park, Taeyoung...
CCS
2007
ACM
16 years 1 months ago
Yet another MicroArchitectural Attack: : exploiting I-Cache
Abstract. MicroArchitectural Attacks (MA), which can be considered as a special form of SideChannel Analysis, exploit microarchitectural functionalities of processor implementation...
Onur Aciiçmez
200
Voted
LCPC
2007
Springer
16 years 1 months ago
Revisiting SIMD Programming
Massively parallel SIMD array architectures are making their way into embedded processors. In these architectures, a number of identical processing elements having small private st...
Anton Lokhmotov, Benedict R. Gaster, Alan Mycroft,...
PACT
2007
Springer
16 years 1 months ago
Support for Fine-Grained Synchronization in Shared-Memory Multiprocessors
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
Vladimir Vlassov, Oscar Sierra Merino, Csaba Andra...
PPOPP
2006
ACM
16 years 25 days ago
A case study in top-down performance estimation for a large-scale parallel application
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
Ilya Sharapov, Robert Kroeger, Guy Delamarter, Raz...