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ITC
1999
IEEE
118views Hardware» more  ITC 1999»
15 years 11 months ago
Logic BIST for large industrial designs: real issues and case studies
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
Graham Hetherington, Tony Fryars, Nagesh Tamarapal...
IPPS
1999
IEEE
15 years 11 months ago
Process Networks as a High-Level Notation for Metacomputing
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
Darren Webb, Andrew L. Wendelborn, Kevin Maciunas
HOTI
2008
IEEE
16 years 1 months ago
Network Processing on an SPE Core in Cell Broadband Engine
Cell Broadband EngineTM is a multi-core system on a chip and is composed of a general-purpose Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs). Its ...
Yuji Kawamura, Takeshi Yamazaki, Hiroshi Kyusojin,...
TCS
2008
15 years 6 months ago
Security types for dynamic web data
We describe a type system for the Xd calculus of Gardner and Maffeis. An Xd-network is a network of locations, where each location consists of both a data tree (which contains scr...
Mariangiola Dezani-Ciancaglini, Silvia Ghilezan, J...
213
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SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
16 years 1 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...