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WSC
1997
15 years 9 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
IJPP
2006
82views more  IJPP 2006»
15 years 7 months ago
Supporting Microthread Scheduling and Synchronisation in CMPs
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
Ian Bell, Nabil Hasasneh, Chris R. Jesshope
AROBOTS
2002
105views more  AROBOTS 2002»
15 years 7 months ago
A Social Robot that Stands in Line
Recent research in mobile robot navigation make it feasible to utilize autonomous robots in service fields. But, such applications require more than just navigation. To operate in...
Yasushi Nakauchi, Reid G. Simmons
VLDB
2002
ACM
129views Database» more  VLDB 2002»
15 years 7 months ago
Optimizing View Queries in ROLEX to Support Navigable Result Trees
An increasing number of applications use XML data published from relational databases. For speed and convenience, such applications routinely cache this XML data locally and acces...
Philip Bohannon, Sumit Ganguly, Henry F. Korth, P....
SEUS
2010
IEEE
15 years 6 months ago
Reactive Clock Synchronization for Wireless Sensor Networks with Asynchronous Wakeup Scheduling
Most of the existing clock synchronization algorithms for wireless sensor networks can be viewed as proactive clock synchronization since they require nodes to periodically synchro...
Sang Hoon Lee, Yunmook Nah, Lynn Choi
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