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CODES
2008
IEEE
15 years 9 months ago
Slack analysis in the system design loop
We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by su...
Girish Venkataramani, Seth Copen Goldstein
CCE
2004
15 years 7 months ago
Designing reactive distillation processes: present and future
The potential benefits of applying reactive distillation (RD) processes are taxed by significant complexities in process development and design. The design problem is formulated i...
C. P. Almeida-Rivera, P. L. J. Swinkels, J. Grievi...
CODES
2004
IEEE
15 years 11 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
ISQED
2005
IEEE
169views Hardware» more  ISQED 2005»
16 years 21 days ago
ASLIC: A Low Power CMOS Analog Circuit Design Automation
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
Jihyun Lee, Yong-Bin Kim
ER
2008
Springer
140views Database» more  ER 2008»
15 years 9 months ago
Design Metrics for Data Warehouse Evolution
During data warehouse design, the designer frequently encounters the problem of choosing among different alternatives for the same design construct. The behavior of the chosen desi...
George Papastefanatos, Panos Vassiliadis, Alkis Si...