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ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 11 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
IADIS
2008
15 years 8 months ago
Design of an Automated System for Clustering Heterogeneous Data
The goal of this work is to study the feasibility of a Heterogeneous Data Classification and Search (HDCS) system and to provide a possible design for its implementing. In order t...
Dorin Carstoiu, Alexandra Cernian, Adriana Olteanu...
TCSV
2010
15 years 2 months ago
High Performance Stereo Vision Designed for Massively Data Parallel Platforms
Abstract--Real-time stereo vision is attractive in many applications like robot navigation and 3D scene reconstruction. Data parallel platforms, e.g. GPU, is often used for real-ti...
Wei Yu, Tsuhan Chen, Franz Franchetti, James C. Ho...
INFOCOM
2006
IEEE
16 years 1 months ago
Design Guidelines for Maximizing Lifetime and Avoiding Energy Holes in Sensor Networks with Uniform Distribution and Uniform Rep
— This paper investigates theoretical aspects of the uneven energy depletion phenomenon recently noticed in sink-based wireless sensor networks. We consider uniformly distributed...
Stephan Olariu, Ivan Stojmenovic
MEMOCODE
2006
IEEE
16 years 1 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...