6239 search results - page 313 / 1248 » From Zinc to Design Model |
229
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DAC
2007
ACM
15 years 11 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
226
Voted
SCA
2007
15 years 9 months ago
2007
In this paper, we present an intuitive interface for interactively posing 3D facial expressions. The user can create and edit facial expressions by drawing freeform strokes, or by...
216
Voted
DAC
2006
ACM
16 years 8 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
179
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SRDS
2007
IEEE
16 years 1 months ago
2007
IEEE
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
211
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CODES
2007
IEEE
15 years 11 months ago
2007
IEEE
Today's MPSoC synthesis and exploration design flows start abstract input specification model captured in a system level design language. Usually this model is created from a...