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FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
16 years 28 days ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
SASP
2009
IEEE
170views Hardware» more  SASP 2009»
16 years 1 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
CHES
2004
Springer
128views Cryptology» more  CHES 2004»
16 years 5 days ago
Long Modular Multiplication for Cryptographic Applications
Abstract. A digit-serial, multiplier-accumulator based cryptographic coprocessor architecture is proposed, similar to fix-point DSP's with enhancements, supporting long modula...
Laszlo Hars
CF
2009
ACM
16 years 1 months ago
Strategies for dynamic memory allocation in hybrid architectures
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
Peter Bertels, Wim Heirman, Dirk Stroobandt
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
15 years 11 months ago
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
U. Girola, A. Picciriello, D. Vincenzoni