127 search results - page 5 / 26 » Generation of Design Suggestions for Coarse-Grain Reconfigur... |
202
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IPPS
2006
IEEE
16 years 19 days ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
168
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
196
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CODES
2006
IEEE
16 years 21 days ago
2006
IEEE
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
242
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FCCM
2011
IEEE
14 years 10 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
209
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AES
2005
Springer
15 years 6 months ago
2005
Springer
Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-...