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DAC
2009
ACM
16 years 8 months ago
Generating test programs to cover pipeline interactions
Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural speci...
Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, ...
VLSID
2009
IEEE
115views VLSI» more  VLSID 2009»
16 years 8 months ago
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
Prabhat Mishra, Mingsong Chen
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
16 years 1 months ago
Functional test generation using property decompositions for validation of pipelined processors
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
Heon-Mo Koo, Prabhat Mishra
ITCC
2003
IEEE
16 years 25 days ago
RDF/XML-based Automatic Generation of Adaptable Hypermedia Presentations
As web information systems tend to mature it has become increasingly important to have an engineered design of such systems. Hera is a design methodology that supports the develop...
Flavius Frasincar, Geert-Jan Houben, Peter Barna, ...
203
Voted
ICC
2009
IEEE
116views Communications» more  ICC 2009»
15 years 5 months ago
Efficient Implementation of Binary Sequence Generator for WiMAX and WRAN on Programmable Digital Signal Processor
In this paper, an efficient design for implementing binary sequence generator on 32-bit instruction execution mode TI TMS320C6416 DSP is presented. The main goal is to achieve high...
Lok Tiing Tie, Ser Wah Oh, K. J. M. Kua