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FCCM
2006
IEEE
107views VLSI» more  FCCM 2006»
16 years 1 months ago
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
Uday Bondhugula, Ananth Devulapalli, James Dinan, ...
205
Voted
FAST
2011
14 years 10 months ago
A Scheduling Framework That Makes Any Disk Schedulers Non-Work-Conserving Solely Based on Request Characteristics
Exploiting spatial locality is critical for a disk scheduler to achieve high throughput. Because of the high cost of disk head seeks and the non-preemptible nature of request serv...
Yuehai Xu, Song Jiang
HIPEAC
2011
Springer
14 years 6 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
SRDS
2006
IEEE
16 years 1 months ago
Topology Sensitive Replica Selection
As the disks typically found in personal computers grow larger, protecting data by replicating it on a collection of “peer” systems rather than on dedicated high performance s...
Dmitry Brodsky, Michael J. Feeley, Norman C. Hutch...
IJVR
2008
106views more  IJVR 2008»
15 years 7 months ago
Improved View Frustum Culling Technique for Real-Time Virtual Heritage Application
Real-time virtual heritage application is normally executed with a high performance computer system. This is due to the complexity and highly computational cost which makes such sy...
Mohd Shahrizal Sunar, Abdullah Mohd Zin, Tengku M....