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DFT
2006
IEEE
105views VLSI» more  DFT 2006»
16 years 1 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
BMCBI
2008
77views more  BMCBI 2008»
15 years 7 months ago
SeqAn An efficient, generic C++ library for sequence analysis
Background: The use of novel algorithmic techniques is pivotal to many important problems in life science. For example the sequencing of the human genome [1] would not have been p...
Andreas Döring, David Weese, Tobias Rausch, K...
EUROPAR
2009
Springer
15 years 11 months ago
Using Hybrid CPU-GPU Platforms to Accelerate the Computation of the Matrix Sign Function
Abstract. We investigate the performance of two approaches for matrix inversion based on Gaussian (LU factorization) and Gauss-Jordan eliminations. The target architecture is a cur...
Peter Benner, Pablo Ezzatti, Enrique S. Quintana-O...
PPDP
1999
Springer
15 years 11 months ago
C--: A Portable Assembly Language that Supports Garbage Collection
For a compiler writer, generating good machine code for a variety of platforms is hard work. One might try to reuse a retargetable code generator, but code generators are complex a...
Simon L. Peyton Jones, Norman Ramsey, Fermin Reig
CODES
2006
IEEE
16 years 1 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha