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» High-level area and power estimation for VLSI circuits
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VLSID
2004
IEEE
128views VLSI» more  VLSID 2004»
16 years 7 months ago
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
16 years 1 months ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan
PCM
2004
Springer
113views Multimedia» more  PCM 2004»
16 years 2 days ago
Low-Power Video Decoding for Mobile Multimedia Applications
This paper proposes a novel low-power video decoding scheme. In the encoded video bitstream, there are quite a large number of non-coded blocks. When the number of the non-coded bl...
Seongsoo Lee, Min-Cheol Hong
VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
16 years 7 months ago
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In [1], we proposed a new switching probability model based on Bayesian N...
Sanjukta Bhanja, N. Ranganathan
VLSID
2007
IEEE
152views VLSI» more  VLSID 2007»
16 years 7 months ago
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...