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IPPS
2010
IEEE
15 years 5 months ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell
IPPS
2010
IEEE
15 years 5 months ago
pFANGS: Parallel high speed sequence mapping for Next Generation 454-roche Sequencing reads
Millions of DNA sequences (reads) are generated by Next Generation Sequencing machines everyday. There is a need for high performance algorithms to map these sequences to the refer...
Sanchit Misra, Ramanathan Narayanan, Wei-keng Liao...
CEC
2010
IEEE
15 years 4 months ago
Improving evolutionary testing by means of efficiency enhancement techniques
TestFul is a novel evolutionary testing approach for object-oriented programs with complex internal states. In our preliminary experiments, it already outperformed some of the well...
Matteo Miraz, Pier Luca Lanzi, Luciano Baresi
ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
16 years 1 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
ICPP
1998
IEEE
15 years 11 months ago
A memory-layout oriented run-time technique for locality optimization
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
Yong Yan, Xiaodong Zhang, Zhao Zhang