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HPCA
2011
IEEE
14 years 11 months ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
LANOMS
2007
IEEE
172views Education» more  LANOMS 2007»
16 years 1 months ago
Implementing and Deploying Network Monitoring Service Oriented Architectures
—Recently there is a growing interest in accessing network measurement and status data across multiple domains, in order to detect eventual network problems which can hinder the ...
Leobino Nascimento Sampaio, Ivo Koga, Rafael Costa...
ICS
2003
Tsinghua U.
16 years 23 days ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
16 years 16 days ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
252
Voted
INFOCOM
1998
IEEE
15 years 11 months ago
Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...
Donpaul C. Stephens, Hui Zhang