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IPPS
2006
IEEE
16 years 1 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
151
Voted
ISCAS
2006
IEEE
101views Hardware» more  ISCAS 2006»
16 years 1 months ago
A cost-effective reconfigurable accelerator for platform-based SOC design
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigu...
Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-M...
245
Voted
KBSE
2006
IEEE
16 years 1 months ago
A Portable Compiler-Integrated Approach to Permanent Checking
Program checking technology is now a mature technology, but is not yet used on a large scale. We identify one cause of this gap in the decoupling of checking tools from the everyd...
Eugen-Nicolae Volanschi
185
Voted
ANCS
2006
ACM
16 years 1 months ago
A practical fast parallel routing architecture for Clos networks
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos network...
Si-Qing Zheng, Ashwin Gumaste, Enyue Lu
219
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CONEXT
2006
ACM
16 years 1 months ago
Towards a versatile transport protocol
In the context of a reconfigurable transport protocol, this paper introduces two protocol instances based on the composition and specialisation of the TFRC congestion control and...
Guillaume Jourjon, Emmanuel Lochin, Patrick S&eacu...
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