857 search results - page 48 / 172 » Implementing a STARI chip |
157
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ASYNC
2007
IEEE
15 years 10 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
171
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
174
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DSD
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
248
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ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
129
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FPL
2008
Springer
15 years 8 months ago
2008
Springer
While there have been many reported implementations of Networks-on-Chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication ...