100 search results - page 8 / 20 » Improved Policies for Drowsy Caches in Embedded Processors |
148
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MICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
166
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SC
2009
ACM
16 years 1 months ago
2009
ACM
The management of shared caches in multicore processors is a critical and challenging task. Many hardware and OS-based methods have been proposed. However, they may be hardly adop...
206
Voted
ICS
2010
Tsinghua U.
15 years 9 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
176
Voted
DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
215
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DAC
2009
ACM
15 years 11 months ago
2009
ACM
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...