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TCAD
2010
88views more  TCAD 2010»
15 years 2 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
IPPS
2009
IEEE
16 years 2 months ago
Handling OS jitter on multicore multithreaded systems
Various studies have shown that OS jitter can degrade parallel program performance considerably at large processor counts. Most sources of system jitter fall broadly into 5 catego...
Pradipta De, Vijay Mann, Umang Mittaly
CODES
2005
IEEE
16 years 1 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
203
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FASE
2006
Springer
15 years 11 months ago
Automated Systematic Testing of Open Distributed Programs
We present an algorithm for automatic testing of distributed programs, such as Unix processes with inter-process communication and Web services. Specifically, we assume that a prog...
Koushik Sen, Gul Agha
BMCBI
2007
166views more  BMCBI 2007»
15 years 7 months ago
PathFinder: mining signal transduction pathway segments from protein-protein interaction networks
Background: A Signal transduction pathway is the chain of processes by which a cell converts an extracellular signal into a response. In most unicellular organisms, the number of ...
Gürkan Bebek, Jiong Yang