328 search results - page 46 / 66 » Improving Performance of Small On-Chip Instruction Caches |
193
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ISLPED
2010
ACM
15 years 6 months ago
2010
ACM
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...
167
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MICRO
2005
IEEE
16 years 7 days ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
192
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PACT
2007
Springer
16 years 24 days ago
2007
Springer
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
142
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CASCON
1996
15 years 8 months ago
1996
The trend in workstation hardware is towards symmetric shared-memory multiprocessors (SMPs). User expectations are for (largely) automatic exploitation of parallelismon an SMP, si...
217
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CODES
2004
IEEE
15 years 10 months ago
2004
IEEE
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...