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» Improving SHA-2 Hardware Implementations
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FPL
2004
Springer
90views Hardware» more  FPL 2004»
15 years 10 months ago
Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation
Abstract. This paper presents a new data representation known as Dual FiXedpoint (DFX), which employs a single bit exponent to select two different fixedpoint scalings. DFX provide...
Chun Te Ewe, Peter Y. K. Cheung, George A. Constan...
TON
2010
87views more  TON 2010»
15 years 1 months ago
Measuring Transmission Opportunities in 802.11 Links
Abstract-- We propose a powerful MAC/PHY cross-layer approach to measuring 802.11 transmission opportunities in WLAN networks on a per-link basis. Our estimator can operate at a si...
Domenico Giustiniano, David Malone, Douglas J. Lei...
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
15 years 10 months ago
Synthesis-for-testability using transformations
- We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and ...
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
AIA
2007
15 years 8 months ago
Embedded harmonic control for dynamic trajectory planning on FPGA
This paper presents a parallel hardware implementation of a well-known navigation control method on reconfigurable digital circuits. Trajectories are estimated after an iterated ...
Bernard Girau, Amine M. Boumaza
ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
16 years 3 months ago
Two dimensional highly associative level-two cache design
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
Chuanjun Zhang, Bing Xue