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ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
16 years 1 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
227
Voted
MICRO
2008
IEEE
114views Hardware» more  MICRO 2008»
16 years 1 months ago
Toward a multicore architecture for real-time ray-tracing
Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting intera...
Venkatraman Govindaraju, Peter Djeu, Karthikeyan S...
IC
2000
15 years 8 months ago
Virtual Campus: A Web-Based Customized Learning Environment
Abstract Virtual Campus is an Internet application in education. It combines the advantages of both group and individual learning approaches based on advanced network technologies....
Ka-po Ma, Michael R. Lyn, Wing-Kay Kan
184
Voted
ICASSP
2008
IEEE
16 years 1 months ago
Distributed stereo image coding with improved disparity and noise estimation
Distributed coding of correlated grayscale stereo images is effectively addressed by a recently proposed codec that learns block-wise disparity at the decoder. Based on the Slepia...
David M. Chen, David P. Varodayan, Markus Flierl, ...
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
16 years 8 days ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...