5523 search results - page 175 / 1105 » Improving application performance with hardware data structu... |
187
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ISCA
1994
IEEE
15 years 11 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
190
Voted
PPOPP
2010
ACM
16 years 4 months ago
2010
ACM
To achieve high-performance on multicore systems, sharedmemory parallel languages must efficiently implement atomic operations. The commonly used and studied paradigms for atomici...
166
Voted
FOCS
2007
IEEE
16 years 1 months ago
2007
IEEE
We present a strongly history independent (SHI) hash table that supports search in O(1) worst-case time, and insert and delete in O(1) expected time using O(n) data space. This ma...
169
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ICDE
1993
IEEE
15 years 11 months ago
1993
IEEE
This paper presents the design and implementation of a transaction manager embedded in a log-structured file system [11]. Measurements show that transaction support on a log-stru...
237
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TVCG
2012
13 years 9 months ago
2012
—This paper presents a volumetric modeling framework to construct a novel spline scheme called restricted trivariate polycube splines (RTP-splines). The RTP-spline aims to genera...