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DATE
2009
IEEE
92views Hardware» more  DATE 2009»
16 years 1 months ago
WCRT algebra and interfaces for esterel-style synchronous processing
—The synchronous model of computation together with a suitable execution platform facilitates system-level timing predictability. This paper introduces an algebraic framework for...
Michael Mendler, Reinhard von Hanxleden, Claus Tra...
DDECS
2009
IEEE
202views Hardware» more  DDECS 2009»
16 years 1 months ago
Asynchronous two-level logic of reduced cost
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
Igor Lemberski, Petr Fiser
DSOM
2007
Springer
16 years 1 months ago
Virtualized Interoperability Testing: Application to IPv6 Network Mobility
Interoperability testing is an inherently distributed task. It connects different implementations together and determines if they interact according to their specifications, prov...
Ariel Sabiguero, Anthony Baire, Antoine Boutet, C&...
AGILEDC
2005
IEEE
16 years 24 days ago
Estimating in Actual Time
In an effort to improve our understanding of the way we work, my team grouped together ideas from various sources to come up with an estimation scheme that avoided the confusing n...
Moses M. Hohman
CIMCA
2005
IEEE
16 years 24 days ago
Automatic Sleep Staging using Support Vector Machines with Posterior Probability Estimates
This paper describes attempts at constructing an automatic sleep stage classifier using EEG recordings. Three different feature extraction schemes were compared together with two...
Steinn Gudmundsson, Thomas Philip Runarsson, Sven ...