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MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
16 years 1 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
HPCA
2005
IEEE
16 years 7 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
16 years 5 days ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
HPCA
2004
IEEE
16 years 7 months ago
Accurate and Complexity-Effective Spatial Pattern Prediction
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas ...
EUROPAR
2008
Springer
15 years 8 months ago
Performance Implications of Cache Affinity on Multicore Processors
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
Vahid Kazempour, Alexandra Fedorova, Pouya Alagheb...