16994 search results - page 3084 / 3399 » Improving the Performance of maxRPC |
210
Voted
HPCA
2004
IEEE
16 years 7 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
180
Voted
HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
216
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HPCA
2001
IEEE
16 years 7 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
222
Voted
CHI
2004
ACM
16 years 7 months ago
2004
ACM
Level of Web experience is often a factor for which researchers attempt to control while conducting experimental studies on Web usability. It is typically measured by some means o...
200
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OSDI
2008
ACM
16 years 7 months ago
2008
ACM
Abstract ? Large enterprise networks consist of thousands of services and applications. The performance and reliability of any particular application may depend on multiple service...