16994 search results - page 3249 / 3399 » Improving the Performance of maxRPC |
192
Voted
IRI
2007
IEEE
16 years 1 months ago
2007
IEEE
Many applications require analyzing vast amounts of textual data, but the size and inherent noise of such data can make processing very challenging. One approach to these issues i...
199
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ISCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
181
Voted
ISCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
196
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ISVLSI
2007
IEEE
16 years 1 months ago
2007
IEEE
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
188
Voted
MICRO
2007
IEEE
16 years 1 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...