6546 search results - page 934 / 1310 » Improving the Performance of the RISE Algorithm |
187
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GLVLSI
2008
IEEE
16 years 2 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
224
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GLVLSI
2008
IEEE
16 years 2 months ago
2008
IEEE
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
211
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ICASSP
2008
IEEE
16 years 2 months ago
2008
IEEE
There has been much recent progress in the technical infrastructure necessary to continuously characterize and archive all sounds, or more precisely auditory streams, that occur w...
201
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ICASSP
2008
IEEE
16 years 2 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
228
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ICASSP
2008
IEEE
16 years 2 months ago
2008
IEEE
This paper shows how to improve Hidden Conditional Random Fields (HCRFs) for phone classification by applying various speaker adaptation techniques. These include Maximum A Poste...