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228
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HIPEAC
2010
Springer
16 years 4 months ago
2010
Springer
Abstract. Multi-core processors with shared last-level caches are vulnerable to performance inefficiencies and fairness issues when the cache is not carefully managed between the m...
213
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ASM
2010
ASM
16 years 4 months ago
2010
ASM
The activities of formal modelling and reasoning are closely related. But while the rigour of building formal models brings significant benefits, formal reasoning remains a major...
200
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ICCD
2007
IEEE
16 years 4 months ago
2007
IEEE
The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper pr...
197
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ICCD
2006
IEEE
16 years 4 months ago
2006
IEEE
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
178
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ICCD
2005
IEEE
16 years 4 months ago
2005
IEEE
Bulk data movement occurs commonly in server workloads and their performance is rather poor on today’s microprocessors. We propose the use of small dedicated copy engines, and p...