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    » Kernel Scheduling in Reconfigurable Computing
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    TRETS
    2010
    105views more  TRETS 2010»
    Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing
    15 years 1 months ago
    Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing
    Download  www.csce.uark.edu
    Miaoqing Huang, Vikram K. Narayana, Harald Simmler...
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    DAC
    2004
    ACM
    103views Computer Architecture» more  DAC 2004»
    Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware
    16 years 7 months ago
    Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware
    Download  www.cs.ucr.edu
    Javier Resano, Daniel Mozos
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    FPGA
    2004
    ACM
    158views FPGA» more  FPGA 2004»
    A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
    15 years 11 months ago
    A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
    Download  vlsi.ee.duth.gr
    In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
    Michalis D. Galanis, George Theodoridis, Spyros Tr...
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    TVLSI
    2002
    130views more  TVLSI 2002»
    HW/SW codesign techniques for dynamically reconfigurable architectures
    15 years 6 months ago
    HW/SW codesign techniques for dynamically reconfigurable architectures
    Download  www.csie.ntu.edu.tw
    Abstract--Hardward/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digitalsystems design. However, no previous work has been carried out ...
    Juanjo Noguera, Rosa M. Badia
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    IPPS
    2006
    IEEE
    124views Distributed And Parallel Com...» more  IPPS 2006»
    Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
    16 years 11 days ago
    Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
    Download  www.cecs.uci.edu
    A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
    Michalis D. Galanis, Grigoris Dimitroulakos, Const...
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