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ASPLOS
2006
ACM
16 years 1 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
16 years 2 days ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
IJRR
2010
113views more  IJRR 2010»
15 years 5 months ago
On the Topology of Discrete Strategies
This paper explores a topological perspective of planning in the presence of uncertainty, focusing on tasks specified by goal states in discrete spaces. The paper introduces stra...
Michael Erdmann
177
Voted
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
16 years 12 days ago
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
ICSE
1999
IEEE-ACM
15 years 11 months ago
Exploiting ADLs to Specify Architectural Styles Induced by Middleware Infrastructures
Architecture Definition Languages (ADLs) enable the formalization of the architecture of software systems and the execution of preliminary analyses on them. These analyses aim at...
Elisabetta Di Nitto, David S. Rosenblum