137 search results - page 9 / 28 » Leakage power modeling and reduction with data retention |
195
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ASPDAC
2006
ACM
16 years 20 days ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
164
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
227
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CHES
2008
Springer
15 years 8 months ago
2008
Springer
We propose a generic information-theoretic distinguisher for differential side-channel analysis. Our model of side-channel leakage is a refinement of the one given by Standaert et ...
148
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SOCC
2008
IEEE
16 years 1 months ago
2008
IEEE
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With s...
154
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EUC
2004
Springer
16 years 2 days ago
2004
Springer
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...