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ISQED
2009
IEEE
115views Hardware» more  ISQED 2009»
16 years 2 months ago
TuneLogic: Post-silicon tuning of dual-Vdd designs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. It is our thesis that variability should be addres...
Stephen Bijansky, Sae Kyu Lee, Adnan Aziz
FPGA
2010
ACM
191views FPGA» more  FPGA 2010»
16 years 2 months ago
Voter insertion algorithms for FPGA designs using triple modular redundancy
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
Jonathan M. Johnson, Michael J. Wirthlin
ISESE
2005
IEEE
16 years 1 months ago
Empirical study design in the area of high-performance computing (HPC)
The development of High-Performance Computing (HPC) programs is crucial to progress in many fields of scientific endeavor. We have run initial studies of the productivity of HPC d...
Forrest Shull, Jeffrey Carver, Lorin Hochstein, Vi...
WCC
2005
Springer
130views Cryptology» more  WCC 2005»
16 years 1 months ago
On the Design of Codes for DNA Computing
In this paper, we describe a broad class of problems arising in the context of designing codes for DNA computing. We primarily focus on design considerations pertaining to the phen...
Olgica Milenkovic, Navin Kashyap
SASN
2003
ACM
16 years 29 days ago
A security design for a general purpose, self-organizing, multihop ad hoc wireless network
We present a security design for a general purpose, selforganizing, multihop ad hoc wireless network, based on the IEEE 802.15.4 low-rate wireless personal area network standard. ...
Thomas S. Messerges, Johnas Cukier, Tom A. M. Keve...