Sciweavers

22 search results - page 3 / 5
» LogTM-SE: Decoupling Hardware Transactional Memory from Cach...
Sort
View
JUCS
2000
120views more  JUCS 2000»
15 years 6 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
16 years 26 days ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
14 years 9 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross
ISCA
1995
IEEE
109views Hardware» more  ISCA 1995»
15 years 10 months ago
Next Cache Line and Set Prediction
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald
MSS
2003
IEEE
130views Hardware» more  MSS 2003»
15 years 11 months ago
zFS - A Scalable Distributed File System Using Object Disks
zFS is a research project aimed at building a decentralized file system that distributes all aspects of file and storage management over a set of cooperating machines interconne...
Ohad Rodeh, Avi Teperman