Sciweavers

116 search results - page 6 / 24
» Logical effort based technology mapping
Sort
View
158
Voted
DATE
2009
IEEE
123views Hardware» more  DATE 2009»
15 years 10 months ago
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis
This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with ...
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De ...
153
Voted
MDM
2004
Springer
15 years 11 months ago
Multi-Protocol Profiles to Support User Mobility Across Network Technologies
Seamless roaming in heterogeneous circuit-switched and IP networks is key for successful migration towards all-IP. The Unified Mobility Manager (UMM) keeps track of users’ locat...
Oliver Haase, Ming Xiong, Kazutaka Murakami
157
Voted
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
15 years 10 months ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
159
Voted
DAC
2006
ACM
16 years 7 months ago
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
ITNG
2006
IEEE
16 years 11 days ago
A Study of Self-Organizing Map in Interactive Relevance Feedback
With the vast amount of potential relevant documents on the Web, a key question for a retrieval system is how to achieve a high accuracy retrieval under current Web setting. The w...
Daqing He