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ICCD
1992
IEEE
83views Hardware» more  ICCD 1992»
15 years 11 months ago
Logical Verification of the NVAX CPU Chip Design
ct Digital's NVAX high-performance microprocessor has a complex logical design. A rigorous simulation-based verification effort was undertaken to ensure that there were no log...
Walker Anderson
SIGPLAN
2002
15 years 6 months ago
On-the-fly model checking from interval logic specifications
Future Interval Logic (FIL) and its intuitive graphical representation, Graphical Interval Logic (GIL), can be used as the formal description language of model checking tools to v...
Miguel J. Hornos, Manuel I. Capel
SBCCI
2009
ACM
131views VLSI» more  SBCCI 2009»
15 years 11 months ago
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and...
Hagen Sämrow, Claas Cornelius, Frank Sill, An...
ENTCS
2008
68views more  ENTCS 2008»
15 years 7 months ago
The Reach-and-Evolve Algorithm for Reachability Analysis of Nonlinear Dynamical Systems
This paper introduces a new algorithm dedicated to the rigorous reachability analysis of nonlinear dynamical systems. The algorithm is initially presented in the context of discre...
Pieter Collins, Alexandre Goldsztejn
LPAR
2010
Springer
15 years 5 months ago
How to Universally Close the Existential Rule
This paper introduces a nested sequent system for predicate logic. The system features a structural universal quantifier and a universally closed existential rule. One nice conseq...
Kai Brünnler