3260 search results - page 479 / 652 » MYSEA Technology Demonstration |
142
Voted
DAC
2008
ACM
16 years 8 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
173
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DAC
2007
ACM
16 years 8 months ago
2007
ACM
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance,...
178
Voted
DAC
1999
ACM
16 years 8 months ago
1999
ACM
The many levels of metal used in aggressive deep submicron process technologies has made fast and accurate capacitance extraction of complicated 3-D geometries of conductors essen...
238
Voted
DAC
2000
ACM
16 years 8 months ago
2000
ACM
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
181
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DAC
2001
ACM
16 years 8 months ago
2001
ACM
Highlighted with the newly released intellectual property (IP) protection white paper by VSI Alliance, the protection of virtual components (VCs) has received a large amount of at...