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ICCAD
2008
IEEE
161views Hardware» more  ICCAD 2008»
16 years 3 months ago
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu ...
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ICCAD
2007
IEEE
160views Hardware» more  ICCAD 2007»
16 years 3 months ago
Approximation algorithm for the temperature-aware scheduling problem
— The paper addresses the problem of performance optimization for a set of periodic tasks with discrete voltage/frequency states under thermal constraints. We prove that the prob...
Sushu Zhang, Karam S. Chatha
ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
16 years 3 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
ICCAD
2005
IEEE
107views Hardware» more  ICCAD 2005»
16 years 3 months ago
Projection-based performance modeling for inter/intra-die variations
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J...
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
16 years 3 months ago
Block-based Static Timing Analysis with Uncertainty
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
Anirudh Devgan, Chandramouli V. Kashyap