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172
Voted
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
16 years 1 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
172
Voted
IWMM
2007
Springer
110views Hardware» more  IWMM 2007»
16 years 1 months ago
Path: page access tracking to improve memory management
Traditionally, operating systems use a coarse approximation of memory accesses to implement memory management algorithms by monitoring page faults or scanning page table entries. ...
Reza Azimi, Livio Soares, Michael Stumm, Thomas Wa...
PPOPP
2005
ACM
16 years 18 days ago
Using multiple energy gears in MPI programs on a power-scalable cluster
Recently, system architects have built low-power, high-performance clusters, such as Green Destiny. The idea behind these clusters is to improve the energy efficiency of nodes. H...
Vincent W. Freeh, David K. Lowenthal
196
Voted
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
16 years 3 days ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
CGO
2003
IEEE
15 years 10 months ago
Optimal and Efficient Speculation-Based Partial Redundancy Elimination
Existing profile-guided partial redundancy elimination (PRE) methods use speculation to enable the removal of partial redundancies along more frequently executed paths at the expe...
Qiong Cai, Jingling Xue