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ISCA
2007
IEEE
126views Hardware» more  ISCA 2007»
16 years 1 months ago
Comparing memory systems for chip multiprocessors
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
Jacob Leverich, Hideho Arakida, Alex Solomatnikov,...
ISVC
2007
Springer
16 years 1 months ago
ChipViz : Visualizing Memory Chip Test Data
This paper presents a technique that allows test engineers to visually analyze and explore within memory chip test data. We represent the test results from a generation of chips al...
Amit P. Sawant, Ravi Raina, Christopher G. Healey
ASAP
2006
IEEE
110views Hardware» more  ASAP 2006»
16 years 1 months ago
Loop Transformation Methodologies for Array-Oriented Memory Management
Abstract – The storage requirements in data-dominant signal processing systems, whose behavior is described by arraybased, loop-organized algorithmic specifications, have an imp...
Florin Balasa, Per Gunnar Kjeldsberg, Martin Palko...
GRID
2005
Springer
16 years 1 months ago
Differential checkpointing for reducing memory requirements in optimized SOAP deserialization
Abstract— Differential Deserialization (DDS) is a SOAP optimization technique wherein servers save checkpoints and parser states associated with portions of previously received m...
Nayef Abu-Ghazaleh, Michael J. Lewis
ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
16 years 1 months ago
Fast, predictable and low energy memory references through architecture-aware compilation
The design of future high-performance embedded systems is hampered by two problems: First, the required hardware needs more energy than is available from batteries. Second, curren...
Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefa...