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DAC
2002
ACM
16 years 8 months ago
A general probabilistic framework for worst case timing analysis
CT The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a...
Michael Orshansky, Kurt Keutzer
DAC
2003
ACM
16 years 8 months ago
Compiler-generated communication for pipelined FPGA applications
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
DAC
2004
ACM
16 years 8 months ago
Accurate pre-layout estimation of standard cell characteristics
With the advent of deep-submicron technologies, it has become essential to model the impact of physical/layout effects up front in all design flows [1]. The effect of layout paras...
Hiroaki Yoshida, Kaushik De, Vamsi Boppana
WWW
2006
ACM
16 years 8 months ago
Capturing RIA concepts in a web modeling language
This work addresses conceptual modeling and automatic code generation for Rich Internet Applications, a variant of Web-based systems bridging the gap between desktop and Web inter...
Alessandro Bozzon, Sara Comai, Piero Fraternali, G...
VLSID
2005
IEEE
132views VLSI» more  VLSID 2005»
16 years 8 months ago
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, ...