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MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
16 years 15 days ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
TCAD
2008
101views more  TCAD 2008»
15 years 7 months ago
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
WSC
1998
15 years 8 months ago
Discrete-Event Simulation for the Design and Evaluation of Physical Protection Systems
This paper explores the use of discrete-event simulation for the design and control of physical protection systems for fixed-site facilities housing items of significant value. It...
Sabina E. Jordan, Mark K. Snell, Marcella M. Madse...
CLUSTER
2006
IEEE
16 years 1 months ago
Designing High Performance and Scalable MPI Intra-node Communication Support for Clusters
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
Lei Chai, Albert Hartono, Dhabaleswar K. Panda
INFOCOM
2006
IEEE
16 years 1 months ago
Designing Low Cost Networks with Short Routes and Low Congestion
— We design network topologies and routing strategies which optimize several measures simultaneously: low cost, small routing diameter , bounded degree and low congestion. This s...
Van Nguyen, Charles U. Martel