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ASPDAC
2001
ACM
126views Hardware» more  ASPDAC 2001»
15 years 11 months ago
A new partitioning scheme for improvement of image computation
Abstract-- Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based ...
Christoph Meinel, Christian Stangier
FMSD
2006
119views more  FMSD 2006»
15 years 7 months ago
Feature interaction detection by pairwise analysis of LTL properties - A case study
A Promela specification and a set of temporal properties are developed for a basic call service with a number of features. The properties are expressed in the logic LTL. Interactio...
Muffy Calder, Alice Miller
TCAD
2008
181views more  TCAD 2008»
15 years 7 months ago
A Survey of Automated Techniques for Formal Software Verification
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
Vijay D'Silva, Daniel Kroening, Georg Weissenbache...
160
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SIGSOFT
2005
ACM
16 years 8 months ago
Fluent temporal logic for discrete-time event-based models
Fluent model checking is an automated technique for verifying that an event-based operational model satisfies some state-based declarative properties. The link between the event-b...
Emmanuel Letier, Jeff Kramer, Jeff Magee, Sebasti&...
COMPSAC
2008
IEEE
16 years 1 months ago
A Probabilistic Attacker Model for Quantitative Verification of DoS Security Threats
This work introduces probabilistic model checking as a viable tool-assisted approach for systematically quantifying DoS security threats. The proposed analysis is based on a proba...
Stylianos Basagiannis, Panagiotis Katsaros, Andrew...