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171
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CGO
2006
IEEE
16 years 13 days ago
A Cross-Architectural Interface for Code Cache Manipulation
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
Kim M. Hazelwood, Robert S. Cohn
CGO
2004
IEEE
15 years 10 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
223
Voted
ASPLOS
2012
ACM
14 years 2 months ago
Providing safe, user space access to fast, solid state disks
Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state...
Adrian M. Caulfield, Todor I. Mollov, Louis Alex E...
170
Voted
CIKM
2007
Springer
16 years 16 days ago
Reusing relational sources for semantic information access
The rapid growth of available data arises the need for more sophisticated techniques for semantic access to information. It has been proved that using conceptual model or ontology...
Lina Lubyte
174
Voted
AINA
2007
IEEE
16 years 22 days ago
How to Study Wireless Mesh Networks: A hybrid Testbed Approach
— Simulation is the most famous way to study wireless an mobile networks since they offer a convenient combination of flexibility and controllability. However, their largest dis...
Alexander Zimmermann, Mesut Günes, Martin Wen...