2805 search results - page 216 / 561 » Modeling Memory for Melodies |
170
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WSC
2004
15 years 8 months ago
2004
We consider the steady state output analysis problem for a process that satisfies a functional central limit theorem. We construct asymptotically valid confidence intervals for th...
246
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SIGMETRICS
1996
ACM
15 years 11 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
187
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CASES
2001
ACM
15 years 10 months ago
2001
ACM
Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM...
236
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IEEEPACT
2009
IEEE
15 years 4 months ago
2009
IEEE
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...
187
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SBACPAD
2006
IEEE
16 years 1 months ago
2006
IEEE
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...